Search - dsp fpga

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[VHDL-FPGA-Verilog] dsp-builder-7.2-crack

Description: 5款altera的FPGA开发板原理图，详细介绍了板子的构成及功能-Altera paragraph 5 of the FPGA development board schematics, detailed information on the composition and functions of board
Platform: | Size: 5120 | Author: 张建 | Hits:

[DSP program] EMIF_COM

Description: 实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口-the interface for TI DSP and Xilinx s FPGAs
Platform: | Size: 1147904 | Author: 贺冲 | Hits:

[Software Engineering] zhangqm

Description: 基于dsp和FPGA软件无线电的研究和设计-Dsp and FPGA-based software radio research and design
Platform: | Size: 2708480 | Author: zc | Hits:

[Remote Control] UartAssist

Description: 在数字信号处理领域用的较多的是DSP和FPGA。DSP的优势源于多数信号处理算法的乘-累加运算都是非常密集的。FPGA通过多极流水线架构也能够用来实现MAC单元，并且FPGA技术可以通过一个芯片上的多级MAC单元来提供更多的带宽，速度可以比数字信号处理芯片快，并且功耗较低。CORD IC算法完全由移位和加法操作完成，因此利用FPGA可以实现更高的运算速度。采用流水线结构在FPGA上实现基于CORD IC的对数变换，可以达到80MHz的处理速度。
Platform: | Size: 596992 | Author: xdj | Hits:

[VHDL-FPGA-Verilog] ug_ram

Description: RAM design for FPGA in verilog
Platform: | Size: 289792 | Author: NguyenViet | Hits:

[DSP program] DSPFPGA

Description: 针对电梯数据采集数目较多和数据处理复杂等特点,提出了基于数字信号处理器(DSP)和现场可编程门阵列(FPGA)的电梯智能数据采集系统。在介绍了系统整体结构及各组成子模块后,给出了模块与器件之间硬件接口设计思路和架构,描述了整个系统的软件框架,设计了DSP、AD采样、网络通信和抗干扰等程序。整个系统在工程应用中易于实现,具有很好的推广价值-n accordance with the characteristic of elevator for the large number of data acquisition and handling data complicated, an el- evator data acquisition system based on digital signal processor (DSP) and field programmable gate array (FPGA) is given. After system structure and modules are introduced, the design of interfaces of the hardware and framework between modules and devices are provided, the software design used in the system is described, the DSP, AD sampling, network communication
Platform: | Size: 179200 | Author: 将建 | Hits:

[DSP program] DSP

Description: 利用TS201超高性能的计算处理能力以及FPGA支持的高速接口交换能力,实现了一种对算法的适应性强、结构扩展方便的通用信号处理板,设计了一种基于该通用信号处理板的米波雷达阵列信号处理系统,并以幅相校正、自适应旁瓣相消的算法实现为例,详细介绍了该阵列信号处理系统算法的实现方法。该系统运行稳定可靠,达到了系统的设计要求。-n this paper,multiple DSPs are adopted to design the array signal processing system.By utilizing the high processing ability of the TS201 and the high-speed data exchange ability supported by FPGA,a general array signal processing system with strong adaptability and easy-expansion ability is fulfilled for radar signal processing.Implementation of the algorithm,such as ASLC and calibration of magnitude and phase,is described in detail.The whole system works well,and meets the requirement of the system...
Platform: | Size: 429056 | Author: 将建 | Hits:

[VHDL-FPGA-Verilog] Hardware_Speedup_DSP_FPGA

Description: 现场可编程门阵列（FPGA）已经不再单纯应用在芯片与系统之间的直接互联层，在软件无线电（SDR）中，FPGA逐渐用做通用运算架构来实现硬件加速单元，在降低成本和功耗的基础上提升性能表现。SDR调制解调器的典型实现包括通用处理器（GPP）、数字信号处理器（DSP）和FPGA。而且，FPGA架构可以结合专用硬件加速单元，用来卸载GPP或DSP。软核微处理器可以结合定制逻辑，扩展其内核，也可以将分立的硬件加速协处理器添加到系统中。此外，还可将通用布线资源放在FPGA中，这些硬件加速单元可以并行运行，进一步增强系统的整体运算输出能力-Field programmable gate array (FPGA) is no longer a simple chip and system used in the direct interconnection between the layers, in the Software Defined Radio (SDR) in, FPGA increasingly used as general-purpose computing architecture to achieve hardware acceleration units to reduce costs in and power consumption based on the performance upgrade. SDR modem to achieve a typical general-purpose processor, including (GPP), digital signal processor (DSP) and FPGA. Moreover, FPGA architecture can be combined with dedicated hardware acceleration units to uninstall GPP or DSP. Soft-core microprocessors can combine custom logic and to expand its core, it can be the separation of hardware-accelerated co-processor added to the system. In addition, resources can also be placed on general-purpose FPGA routing, these hardware acceleration units can be run in parallel, to further enhance the overall computing system, the output capacity
Platform: | Size: 261120 | Author: gg | Hits:

[VHDL-FPGA-Verilog] 1111111

Description: 16位定点FFT-DSP的FPGA实现-16-bit fixed-point FFT-DSP for FPGA realization
Platform: | Size: 3834880 | Author: hievery11 | Hits:

[Program doc] rjwxdpt

Description: 软件无线电技术是用于卫星导航和第三代移动通信(3G) 数据处理和计算的最优解决方案。运用基于FPGA的So PC 嵌入式设计方法构造软件无线电系统,提高了对动态实时信号的处理能力。设计完成无线通信体系结构,以及ADC 模数转换,数字下变频,CPU 中央处理器,DSP 运算单元,PCI 桥以及数据控制等模块的详细组成。相对于目前常规系统,该系统在功耗和体积方面可节省30 以上,对高速数据流的处理和计算能力有显著提高,可以应用于Cellular/ PCS 基站,GPS 抗干扰接收机,相控阵接收机,频谱分析和3G无线通信等领域。-Software radio technology is used for satellite navigation and third-generation mobile communication (3G) data processing and computing the optimal solution. So PC using FPGA-based embedded design methods to create software-defined radio system to improve the dynamic real-time signal processing capabilities. Wireless communications architecture design is completed and the ADC analog-digital conversion, digital down conversion, CPU CPU, DSP computing unit, PCI bridge, and data control module, the detailed composition. Relative to the current conventional systems, the system can save power consumption and size are more than 30 of the high-speed data stream processing and computing power has significantly increased, can be applied to Cellular/PCS base stations, GPS anti-jamming receivers, phased array receivers, spectrum analysis, and 3G wireless communications and other fields.
Platform: | Size: 516096 | Author: x | Hits:

[Compress-Decompress algrithms] Sp3A-DSP-1800A-Starter-Schematic-Rev1

Description: spartan1800A的原理图和资料，有了它的，我们的设计就会快捷方便许多了-Spartan-3A DSP FPGA Board and Kit Documentation.
Platform: | Size: 576512 | Author: liaolain | Hits:

[matlab] matlab_dsp_building

Description: matlab dsp building fpga-matlab dsp building
Platform: | Size: 1401856 | Author: 吴小平 | Hits:

[DSP program] DSP

Description: DSP硬件论文集，包含22篇DSP相关论文，caj格式。都是花银子买来的。 DSP与点阵式LCD显示器的接口设计.caj DSP体系结构在提高实时信号处理方面的作用.caj DSP器件的原理及应用.caj DSP在机械设备故障诊断中的应用.caj DSP应用的结构和发展方向.caj DSP技术及其应用讲座(六)──数字通信用数字调制解调器中的DSP技.caj DSP技术及其应用讲座第7讲语音识别及其DSP实现.caj DSP技术及其应用讲座第三讲数字信号处理器的发展及其特点.caj DSP技术及其应用讲座第二讲数字信号处理的理论基础.caj DSP技术的发展与应用.caj DSP结构(中).caj DSP还是微处理器.caj TMS320C2XXDSP芯片的软件开发与调试方法.caj Windows环境下DSP的开发和语音分析工具SAC.caj 一种基于DSP的高速数据获取及处理系统.caj 一种基于PC机的多DSP系统设计.caj 一种高速PC-DSP控制系统.caj 基于PLD的DSP设计方案.caj 带有DSP芯片的新型实时数字图像处理系统.caj 数字信号处理器(DSP)的发展及市场动向.caj 数字通信用数字调制解调器中的DSP技术.caj 用可再配置FPGA实现DSP功能.caj -DSP hardware, Proceedings, including the 22 DSP-related papers, caj format. Are the flowers of silver bought.
Platform: | Size: 1060864 | Author: 刘伟 | Hits:

[Industry research] DSP

Description: 。本文针对三电平高压变频器控制要求的特点，设计了基于DSP 和FPGA 的控制电路。利用DSP 进行高速浮点计算，满足实时控制的要求；FPGA 并行执行程序，实现了多路触发信号的同时控制，而且由于采用了硬件电路完成计算，提高了控制系统的可靠性-. In this paper, three-level voltage inverter control requirements of the features, design and FPGA-based DSP control circuit. High-speed floating-point calculations using DSP to meet the requirements of real-time control FPGA parallel implementation of the program, realized the trigger signal, while multi-channel control, and because use of the hardware circuitry to complete the calculation and improve the reliability of the control system
Platform: | Size: 320512 | Author: scnu | Hits:

[VHDL-FPGA-Verilog] BPSK_track_10.23M_BD_IF46.52MHz

Description: in tracking programm，actualize communications between DSP and FPGA Besides produce ahead code present code late code and correlation integral result-communications between DSP and FPGA Besides produce ahead code present code late code and correlation integral result
Platform: | Size: 3322880 | Author: laonong | Hits:

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[Special Effects] video_process_base_on_DSPandFPGA

[VHDL-FPGA-Verilog] dsp-builder-7.2-crack

[DSP program] EMIF_COM

[Software Engineering] zhangqm

[Remote Control] UartAssist

[VHDL-FPGA-Verilog] ug_ram

[DSP program] DSPFPGA

[DSP program] DSP

[VHDL-FPGA-Verilog] Hardware_Speedup_DSP_FPGA

[VHDL-FPGA-Verilog] 1111111

[Program doc] rjwxdpt

[Compress-Decompress algrithms] Sp3A-DSP-1800A-Starter-Schematic-Rev1

[matlab] matlab_dsp_building

[DSP program] DSP

[Industry research] DSP

[VHDL-FPGA-Verilog] BPSK_track_10.23M_BD_IF46.52MHz

[VHDL-FPGA-Verilog] xapp753

[DSP program] DSP-FPGA1

[VHDL-FPGA-Verilog] i2c

[VHDL-FPGA-Verilog] FPGA

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